FPGA Competency: Design, coding, verification, VHDL
Posted: Wed Aug 11, 2010 10:20 am
Many designs take the path of programmable mixed signal platforms, to mitigate their design and verification risks by early prototyping and validation of their high volume ASIC designs. These platforms provide faster turn around time for validating proof of concept of new IP, integration of new IP etc. In addition, some designs adopt standard design platforms because of the dexterity it offers in capturing various type of signal and adding unique requirements that address a specific market or design criterion.
The Enventure team has in-depth experience in High speed timing critical data acquisition with mixed signal design capability and which can be offered as standalone service or as integrated solution.
Service areas include:
* Planning, Specification and Device Selection
* Core and IP Strategy
* Design, Coding, and Verification (VHDL, Verilog, SystemC).
* Place-and-Route and Timing Optimization
* FPGA-Based System board design and debug capability.
* Concept Validation and FPGA to ASIC Migration.
* Board Support Package (BSP) for platforms
Sample of team expertise:
* Memory and Peripherals
* High Speed ADC and DAC Implementations
* High Speed Interfaces Support
* Security Algorithm Implementations
* ASIC / IP Proof of Concept Testing on FPGA
The Enventure team has in-depth experience in High speed timing critical data acquisition with mixed signal design capability and which can be offered as standalone service or as integrated solution.
Service areas include:
* Planning, Specification and Device Selection
* Core and IP Strategy
* Design, Coding, and Verification (VHDL, Verilog, SystemC).
* Place-and-Route and Timing Optimization
* FPGA-Based System board design and debug capability.
* Concept Validation and FPGA to ASIC Migration.
* Board Support Package (BSP) for platforms
Sample of team expertise:
* Memory and Peripherals
* High Speed ADC and DAC Implementations
* High Speed Interfaces Support
* Security Algorithm Implementations
* ASIC / IP Proof of Concept Testing on FPGA